The present invention relates to methods for fabricating semiconductor devices including processes of implanting ions into semiconductor layers at tilt angles.
As a method for forming a doped layer in a semiconductor layer, a technique of implanting ions into the semiconductor layer at a tilt angle of about 40 degrees with respect to the normal to the upper surface of the semiconductor layer (hereinafter referred to as large-angle-tilt ion implantation) has been known to date. The large-angle-tilt ion implantation is used in, for example, a process for fabricating a transistor having a lightly doped drain (LDD) structure. In this process, the large-angle-tilt ion implantation performed on a semiconductor layer on which a gate electrode has been formed allows the formation of a shallow n+layer extending to a region of the semiconductor layer under the gate electrode. This is disclosed in, for example, Japanese Laid-Open Publication No. 6295875 (pp. 3-5, FIG. 1)
Hereinafter, a known large-angel-tilt ion implantation technique will be described with reference to FIG. 9. FIG. 9 is a cross-sectional view showing a known process step of performing large-angle-tilt ion implantation in a process for fabricating a semiconductor device.
The semiconductor device shown in FIG. 9 includes, in an upper part of a silicon substrate 101, a p-type region 102, an n-type region 103 located at a side of the p-type region 102 and an insulating film 104 for transistor isolation provided between the P-type region 102 and the n-type region 103. The upper surface of the n-type region 103 is covered with a photoresist layer 114 with a thickness of 1.0 xcexcm. The upper surface of the p-type region 102 is exposed with a gate insulating film 105 and a gate electrode 106 formed thereon.
In this state, ions of an n-type impurity are implanted into the p-type region 102 using the gate electrode 106 and the photoresist layer 114 as a mask, thereby forming an nxe2x88x92layer 115 having an LDD structure. These ions are implanted with the silicon substrate 101 rotated. In this case, the ion implantation is performed with tilt, so that an nxe2x88x92 layer 115 is formed to overlap with the gate electrode 106 in part of the p-type region 102 located under the edge of the gate electrode 106.
However, with the downsizing of the semiconductor device, the gate electrode 106 and the photoresist layer 114 come closer to each other, thus arising the following problems.
In the process step shown in FIG. 9, the ions are implanted at a tile angle 9: with respect to the vertical direction (the normal) to the upper surface of the silicon substrate 101. In this process step, if the thickness of the photoresist 114 formed on the n-type region 103 is large, emission of the ions with tilt is blocked partly by the photoresist 114. As a result, the impurity also cannot be implanted into part of a region to be the nxe2x88x92layer 115.
In particular, if the direction of the ion implantation is greatly tiled with respect to the normal to the substrate, ions are less implanted into part of the p-type region 102 under the gate electrode 106. As a result, an overlap between the gate electrode 160 and the nxe2x88x92layer 115 is less likely to be formed.
However, if the thickness of the photoresist layer 114 is reduced to implant the impurity into a region to be the nxe2x88x92layer 115, the impurity might penetrate through the photoresist layer 114 to reach the n-type region 103 and other regions.
It is therefore an object of the present invention to provide a method for fabricating a semiconductor device capable of being further reduced in size.
Specifically, a first inventive method for fabricating a semiconductor device includes the steps of: a) forming a gate insulating film and a gate electrode over a first transistor region defined in a semiconductor substrate; b) forming, on the semiconductor substrate, a hard mask having an opening for exposing the first transistor region therein, after the step a) has been performed; c) implanting an impurity into the semiconductor substrate in the manner of large-angle-tilt ion implantation, using the gate electrode and the hard mask as a mask for ion implantation; and d) removing the hard mask, after the step c) has been performed.
With this method, a hard mask having a high ability of preventing impurity implantation is used as a mask for ion implantation, so that the mask for ion implantation can be made thin. Accordingly, the direction of ion implantation can be set closer to the horizontal direction, resulting in that ions can be implanted into a wider region with a shallower junction depth.
In the step b), the thickness of the hard mask and the width of the opening of the hard mask are preferably defined such that the impurity reaches a region under the gate electrode during the large-angle-tilt ion implantation in the step c).
In part of the semiconductor substrate, a second transistor region may be provided at a side of the first transistor region with an insulating film for transistor isolation interposed therebetween, and in the step b), the hard mask may be formed to cover the second transistor region.
The hard mask is preferably one out of a BPSG film, a PSG film and a silicon nitride film.
The first inventive method preferably further includes the step e) of rounding off an upper edge of the hard mask, thereby making the hard mask to have a tapered edge, between the steps b) and c). Then, ions can be implanted into a wider region.
In the step e), isotropic etching may be performed, thereby making the hard mask to have the tapered edge
In the step e), heat treatment may be performed, thereby making the hard mask to have the tapered edge.
A second inventive method for fabricating a semiconductor device includes the steps of: a) forming a gate insulating film and a gate electrode over a first transistor region defined in a semiconductor substrate; b) forming a resist layer on the semiconductor substrate; c) silylating at least part of the resist layer other than a region of the resist layer located on the first transistor region, thereby forming a silylated region; d) removing at least part of the region of the resist layer other than the silylated region, thereby forming a silylated resist pattern; and e) implanting an impurity into the semiconductor substrate in the manner of large-angle-tilt ion implantation, using the silylated resist pattern as a mask for ion implantation.
With this method, a silylated region having a high ability of preventing impurity implantation is used as a mask for ion implantation, so that the mask for ion implantation can be made thin. Accordingly, the direction of ion implantation can be set closer to the horizontal direction, resulting in that ions can be implanted into a wider region with a shallower junction depth.
The second inventive method preferably further includes the step of oxidizing the silylated region, between the steps d) and e). Then, the silylated layer has a higher ability of preventing ion implantation. As a result, the thickness of the mask for ion implantation
FIGS. 1A through 1F are cross-sectional views showing process steps up to a process step of forming an nxe2x88x92layer having an LDD structure in a process for fabricating a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view for describing an ion implantation technique for forming an nxe2x88x92layer 13 in the first embodiment, for comparison to a known ion implantation technique.
FIGS. 3A through 3C are cross-sectional views showing process steps up to a process step of forming an nxe2x88x92layer having an LDD structure in a process for fabricating a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view for describing an ion implantation technique for forming an nxe2x88x92layer 13 in the second embodiment, for comparison to the ion implantation technique in the first embodiment.
FIGS. 5A through 5C are cross-sectional views showing process steps up to a process step of forming an nxe2x88x92layer having an LDD structure in a process for fabricating a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a cross-sectional view for describing an ion implantation technique for forming an nxe2x88x92 layer 13 in the third embodiment, for comparison to the ion implantation technique in the first embodiment
FIGS. 7A through 7F are cross-sectional views showing process steps up to a process step of forming an nxe2x88x92layer having an LDD structure in a process for fabricating a semiconductor device according to a fourth embodiment of the present invention.
FIG. 8 is a cross-sectional view for describing an ion implantation technique for forming an nxe2x88x92layer 55 for comparison to the known ion implantation technique.
FIG. 9 is a cross-sectional view showing a process step of performing large-angle-tilt ion implantation in a process for fabricating a known semiconductor device.